However, since in most applications the transmitter clock and the receiver clock are not running at exactly the same frequency, an additional clock drift exists which reduces the performance in the receiver. This is particularly true for wireless communication systems in which the time frame length is comparatively long, for example in cases in which one frame includes more than one hundred FFT (Fast Fourier Transformation) blocks, each FFT block including several hundred symbols. For example high data rate single carrier wireless systems using SC-FDE (single carrier frequency domain equalization), the frame length might include for example 256 FFT blocks, each FFT block including 512 symbols. When the clock drift between the transmitter clock and the receiver clock is 10 ppm and the length of a data part in a frame is 32000 symbols, the sampling drift within the frame is about 0.32 symbols, which shows that a clock drift compensation or symbol tracking is necessary.
The symbol tracking or clock drift compensation could be realized using a correlation of a time domain sequence, but this would result in additional overhead. In addition, a high oversampling rate, i.e. an ADC sampling rate which is high compared to the symbol rate, would be necessary, resulting in a more complex structure.